DRAMs (Dynamic Random Access Memories) are volatile memories and have a structure of storing information in capacitors in memory cells. Therefore, with the passage of time after data have been written in the cells, electric charge will leak and information will be lost. Accordingly, the data written in there are refreshed within a fixed time.
For example, the data retention time guaranteed for 512 Mbit DDR SDRAMs is generally 64 ms, and to maintain data, a refresh operation needs to be performed within 64 ms for 32768 ROW lines.
In addition, semiconductor devices, such as DRAMs, have limited longevities to carry current and their functional characteristics deteriorate as the current carrying time increases. Eventually, semiconductor devices will become unable to satisfy guaranteed standard values and reach the end of their longevities.
One of the characteristics which is related to deterioration of DRAMs is data retention time. DRAMs have a sufficient margin for their guaranteed standard values of the data retention time immediately after they start carrying current; however, the margin becomes smaller as the current carrying time increases, and DRAMs reach the end of their longevities when their data retention time becomes shorter than the guaranteed standard value.
Prior arts related to the present invention include technologies disclosed in the following patent documents. Accordingly, Japanese Laid-open Patent Publication No. 06-333387 discusses a technique that a refresh period monitor circuit for DRAM performs selecting a refresh cycle on the basis of the decision result of a refresh period decision unit. Japanese Laid-open Patent Publication No. 2002-269979 discusses a technique that a semiconductor substrate including a plurality of memory cells performs setting a refresh period of the memory cell monitoring the information holding voltage. Japanese Laid-open Patent Publication No. 2007-48347 discusses a technique that a data recording device including a memory cell array performs refreshing at a time interval which is shorter than a data hold time.